I am interested in the Design of Very Large Scale Integration (VLSI) circuits and systems, the development and use of Computer Aided Design (CAD) tools in VLSI Design, and the use of new technologies such as Java to enhance VLSI and Engineering Education.

Here is a copy of my full Vitae.

Current Projects

• A Hardware-Accelerated Maze Router
• CADAPPLETS - Applets for Visualizing VLSI CAD Algorithms

• High-Level Synthesis of VLSI Systems
• Visual models of VLSI microarchitecture

• “Experience with the CADAPPLETS Project”, Proceedings International Conference on Microelectronics Systems Education, June 2007.
  
• “An FPGA-Based Accelerator for Detailed Maze Routing” (poster, with J. Lavine), International Symposium on FPGAs, February 2007.
  
• "Teaching Computer Organization with HDLs – An Incremental Approach”, Proceedings International Conference on Microelectronics Systems Education, June 2005.
  
• "L3: An FPGA-Based Multilayer Maze Routing Accelerator" (draft preprint), Microprocessors and Microsystems, Vol, 29, No. 2-3, pp. 87-97, March 2005.
  
• "FPGA Implementation of a Multilayer Maze Router", Proceedings 6th Annual Military and Aerospace Programmable Logic Device (MAPLD) International Conference, September 2003.
• "CADAPPLETS: Visualization of VLSI CAD Algorithms"Proceedings 2003 International Conference on Visual Languages and Computing, September 2003. 
• " FPGA Implementation of a Maze Routing Accelerator "Proceedings International Conference on Field-Programmable Logic and Applications, September 2003. 
• "Integrating Digital, Analog, and Mixed-Signal Design in an Undergraduate Curriculum" (with D. Rich), Proceedings International Conference on Microelectronics Systems Education, June 2003. J. A. Nestor, btorbield-Programmable Logic and Applications, September 
• "Analog and Mixed-Signal Design in an Junior Electronics Course Sequence" (with D. Rich), Proceedings ASEE Annual Conference, June 2003. 
• "Animation of VLSI CAD Algorithms: A Case Study" , Proceedings ASEE Annual Conference, June 2002. 
• "Adding Analog and Mixed-Signal Concerns to a Digital VLSI Course" (with D. A. Rich), Proceedings ASEE Annual Conference, June 2002. 
• "A New Look at Hardware Maze Routing"Proceedings Great Lakes Symposium on VLSI, pp. 142-147, April 2002. 
• "Web-Based Visualization Tools for Teaching VLSI CAD Algorithms" , Proceedings 2001 International Conference on Microelectronic System Education, pp. 100-101, June 2001. 
• "SALSA: A New Approach to Scheduling with Timing Constraints," (with G. Krishnamoorthy), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 8, pp. 1107-1122, August 1993. 
• "SALSA II: Improved Transformational Scheduling for High-Level Synthesis" (with M. Rhinehart), Proceedings IEEE International Symposium on Circuits and Systems, pp. 1678-1681, May 1993.
• "J. A. Nestor and V. Tamas, "Exploiting Scheduling Freedom in Controller Synthesis", Sixth International Workshop on High-Level Synthesis , Laguna Beach, California, pp. 74-86, November 1992.
• "Visual Register-Transfer Description of VLSI Microarchitectures" , IEEE Transactions on VLSI Systems, Vol 1, No. 1, pp. 72-76, March 1993.
• "Allocation using an Extended Binding Model" , Proceedings 29th Design Automation Conferance, pp. 279-284, June 1992.